The present invention relates, in general, to the field of computer data switching systems. More particularly, the present invention relates to a data communication system utilizing a scalable, non-blocking, high bandwidth central memory controller and method employing a pipelined, time division multiplexed ("TDM") bus in combination with high speed dual-ported memory buffers and link list technology.
"Fibre Channel" is the name given to a set of standards developed by the American National Standards Institute ("ANSI") which defines certain protocols for information transfer. Fiber Channel devices are individually known as "nodes", each of which has at least one "port" to provide access thereto. The components that then connect two or more ports are denominated as a "topology". Each port uses a pair of "fibres" (electrical wires or optical strands), one to carry information into the port and another to carry it out of the port. The fibre pair is known as a "link". The information transmitted over a link is transferred in indivisible units called "frames". The Fibre Channel standard permits dynamic interconnections between nodes through ports connected by means of a "switch" or "router" (also sometimes referred to as a "fabric") and it is possible, therefore, for any node to communicate with any other node through the "switch" or "router".
Among the techniques which have heretofore been utilized to provide switching capabilities for high speed ports are cross point switching, input queuing and output queuing. A fundamental disadvantage of cross point (or "switched topology") switching is that only one connection at a time can exist to any particular output. Thus, for example, if ports 1 and 2 are in connection and port 3 receives a frame for port 1, port 3 must wait until port 1 becomes available before it can transmit the frame. If, as in this instance, a frame is "waited" and a subsequent frame destined for port 4 is received, even though port 4 may be available, the frame is "blocked" at port 3 until the frame for port 1 is ultimately delivered.
Input queuing is similar in some respects to cross point switching in that it exhibits similar blocking characteristics. In this regard, frames for output ports are buffered at the input and are only delivered when the desired output becomes available. As a consequence, any subsequent frames have the potential to be blocked by the previous frame. On the other hand, output queuing overcomes the blocking problems associated with the cross point switching and input queuing techniques. However, the bandwidth required for the cutput buffer must equal the sum of all possible inputs. For example, a switching system with sixty four 100 MByte/second ports must ensure that each output port is able to sustain 6.3 GByte/second of bandwidth to provide for a non-blocking architecture.
In an attempt to alleviate certain of the problems inherent in the preceding switching architectures, at least one asynchronous transfer mode ("ATM") approach has utilized a TDM bus with wide central memory. However, the architecture proposed also exhibits several critical limitations in that ATM, through the use of fixed cell length, does not have to address the issue of variable length frames and, since the memory width equals the cell length, no horizontal linking of buffers is required. Also, the number of TDM slots is equal to two times the number of ports and each port is allocated an input and an output slot and does not perform input and output during the same TDM slot because the memory is not dual ported. Thus, either the memory word must be twice as wide or the TDM cycle must be half the time to sustain the same total bandwidth.